To date, SoC technology such as FPGAs  have been investigated in the acceleration of many compute-intensive algorithms including image/graphics and physics algorithms, however, the high data-dependencies between PC processors and dedicated FPGA devices has limited their success and exhibited low acceleration performance . Recent FPGA platforms now support significantly faster data interfaces between PC processors, faster clocks speeds and richer embedded features, and are emerging as a key valued computational component in modern SoC computer architectures . In addition, advances in Graphical Processing Units (GPUs)  have also opened new opportunities for the acceleration of regular data-intensive computing tasks. These advances facilitate the novel use of FPGAs and GPUs for the acceleration of data-intensive computing operations such as steganography.
The aim of this research project is to investigate the development of a novel generic hardware architecture which will support the acceleration of a variety of steganography algorithms. The outcome of the PhD research will be the creation of a novel architecture for FPGAs which will allow algorithms to be swapped on and off the FPGA dynamically during execution (partial reconfiguration); addressing the flexibility and acceleration requirements to support future and emerging advances in steganography algorithms. A key aspect of the work will focus on managing the runtime data and data-reconfiguration of accelerated algorithms. The project will be evaluated by comparing the acceleration speed performance of algorithms running on a GPU against the FPGA-based system.
 Harkin J, Morgan F, Hall S, Dudek P, Dowrick T, McDaid L J; “Reconfigurable Platforms & the Challenges for Large-Scale Implementations of SNNs”, IEEE International Conference on Field Programmable Logic Applications (FPL), Heidelberg, Sept, pp. 483 - 486, 2008
 Nvidia http://www.nvidia.co.uk/
The PhD project will have access to a Xilinx Virtex-4 multi-FPGA platform and Nvidia GPU graphics card, and a large suite of Agilent logic analyser/oscilloscope and IP-core debugging instrumentation. Access to the latest Nvidia and Xilinx ISE, EDK and System Generator tools will also be made available.
First Supervisor: Harkin, J Dr
Second Supervisor: Condell, J Dr
Third Supervisor: Curran, K Dr
Collaboration: This project does not involve collaboration with another establishment