The project aims to contribute towards the exploration of a new brain-inspired computing architecture comprised of neurons and synapses. In particular, the project will explore the facilitation of a novel fault tolerant interconnect architecture using Network-on-Chip (NoC) technology  and online built-in self-test strategies [2-3] to provide repairable synapse interconnect between large numbers of neurons.
The last fifty years has witnessed considerable neural networks (NN) research resulting in a range of architectures, learning algorithms and applications. Spiking Neural Networks (SNNs) differ from conventional artificial NN models as information is transmitted by the means of spikes. Software simulations of such network topologies and connection strategies face the problem of scalability in that biological computing systems are inherently parallel in their architecture whereas commercial PCs are based on sequential processing architectures making it difficult to assess the efficiency of these models to solve complex problems. When implemented on hardware, SNNs have the advantage of computational speed over software simulations and can take full advantage of their inherent parallelism, becoming appropriate for real-time applications. However, there are many common challenges which must be overcome if SNNs realised on hardware are to succeed in accommodating the deployment of computational applications. A major challenge is the development of efficient hardware implementation architectures that can support large scale realisations. In particular the current problem of inter-neuron connectivity is prohibiting the implementation of biological scale SNNs as the rapid increase in the ratio of fixed connections to the number of neurons is self-limiting network sizes . Moreover, there is a need to develop reliable interconnect  that can adapt to faults and maintain communication and in effect, perform self-repair. This challenge is further compounded with constraints such as low area/power and minimal intrusion on the runtime system.
The proposed PhD research builds on current work within the University of Ulster where analogue spiking neuron cells and low area/power Network-on-Chip routers have been developed . The existing research has focused on the creation a new Field Programmable Neural Network (EMBRACE) [7-8] hardware architecture that supports the implementation of large-scale Spiking Neural Network applications. The proposed PhD will extend the EMBRACE research by investigating the development of a novel online Built-in Self-Test and Repair (BISTR) strategy for NoCs which will advance the reliability of large scale neural systems. Current research has developed efficient runtime routing algorithms for the NoC  with high throughput however, the key challenges in this project is to develop a BISTR strategy which has minimal impact on the NoC throughput and overall area/power budget. In particular, some of the questions that will be answered in this research include: can the NoC status be monitored in real-time with minimal disruption to traffic throughput? Can a fault be sensed? What level or classification of faults can be made (wire, circuit, logical, component level)? To what degree can repair be made (re-wire or redundancy)? Moreover, the research will identify the upper bounds on reliability within the context of the EMBRACE architecture. The successful student will be located at the Intelligent Systems Research Centre on the Magee campus of the University of Ulster.
The practical outcome of the research will be the creation of a novel online Built-in Self-Test and Repair (BISTR) strategy for NoCs which will support the development of brain-inspired computing systems. Also, results from benchmark applications will demonstrate its potential as a reliable platform that can compute high density networks in real time under the presence of faults.
 Agarwal, A, Iskander C, Shankar R; "Survey of network on chip (NoC) architectures & contributions", Journal of Engineering, Computing and Architecture, 3, pp. 21-27, 2009
 Yu Q, Ampadu P.; “Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip,” ACM/IEEE International Symposium on Networks-on-Chip, Washington, pp.145–154, 2010
 Ituero P, Lopez-Vallejo M, Marcos M, Osuna C, "On-chip Monitoring: A Light-Weight Interconnection Network Approach," 14th IEEE Euromicro Conference on Digital System Design (DSD), pp.619-625, 2011
 Harkin J, Morgan F, Hall S, Dudek P, Dowrick T, McDaid L J; “Reconfigurable Platforms & the Challenges for Large-Scale Implementations of SNNs”, IEEE International Conference on Field Programmable Logic Applications (FPL), Heidelberg, Sept. 8th-10th, pp. 483 - 486, 2008
 Kahng AB., "Design Challenges at 65nm and Beyond", DATE pp. 1 - 2, 2007
 Carrillo S, Harkin J, McDaid L, Morgan F; "An Efficient, High-throughput Adaptive NoC Router for Large-scale Spiking Neural Network Hardware Implementations", International Conference on Evolvable Systems - From Biology to Hardware, Springer LNCS, Sept 2010 (BEST PAPER AWARD)
 Harkin J, Morgan F, McDaid L, Hall S, McGinley B, Cawley S; “A Reconfigurable and Biologically Inspired Paradigm for Computation using Networks-on-chip and Spiking Neural Networks”, International Journal of Reconfigurable Computing, Special Issue, Hindawi Publisher, vol. 2009, pp. 1-13, 2009
 Cawley S, Morgan F, McGinley B, Pande S, McDaid L, Carrillo S, Harkin J; “Hardware Spiking Neural Network Prototyping and Application”, Journal of Genetic Programming and Evolvable Machines: Special Issue on Evolvable Hardware Challenges, Vol. 12(3), Springer, pp. 257-280, 2011
 Carrillo S, Harkin J, McDaid L, Pande S, Cawley S, Morgan F; "Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations", 21st International Conference on Artificial Neural Networks (ICANN), LNCS, Vol 6791, pp. 77-84, Finland, June 14-17th, 2011 (BEST PAPER AWARD)
The PhD project will have access to a modern Xilinx Virtex-4 multi-FPGA platform, and a large suite of Agilent logic analyser/oscilloscope and IP-core debugging instrumentation. Access to the latest Xilinx ISE, EDK and System Generator tools will also be made available.
Contact for further information
Dr. Jim Harkin (firstname.lastname@example.org)
First Supervisor: Harkin, J Dr
Second Supervisor: McDaid, L Dr
Third Supervisor: Maguire, L Prof
Collaboration: This project does not involve collaboration with another establishment